A typical conventional dynamic random-access memory (DRAM) 5 is shown in FIG. 4, and each portion of the signals, the waveform of the data, and the timing during memory access in this DRAM are shown in FIG. 5.
When data is read from the DRAM, a row address strobe signal RAS.sub.-- and column address strobe signal CAS.sub.-- are supplied along with the memory address signal.
First, by enabling the RAS.sub.-- signal of FIG. 5(A), along with completing the precharge of each bit line in memory array 100, a slightly delayed row address signal BX.sub.i shown in FIG. 5(B) is read into an X-address decoder (not shown) of the row address system, and the designated row's word line WLi is activated by this row address signal as shown in FIG. 5(C). By activating word line WL.sub.i, the stored information (data) in each memory cell MC connected to this word line is read out on a corresponding bit line BL as shown in FIG. 5(D). Then the read data is input, together with complementary data on a complementary bit line BL.sub.--, to each bit line's sense amplifier SA and differentially amplified there.
On the other hand, when a column address signal BY.sub.j is input or latched in a Y-address buffer 102 at the prescribed timing shown in FIG. 5(E), an address transition detector (ATD) circuit 104 operates in response.
ATD circuit 104 houses circuits that generate an ATD pulse, an FY pulse, an MA pulse, and an MAEQ pulse. First, ATD circuit 104 generates, in an internal unit, an ATD pulse shown in FIG. 5(G) in response to a transition or change of the input column address signal BY.sub.j. Next, in response to the rise and fall of the ATD pulse, it outputs an FY pulse that determines the activation time of a Y-address line YS and the enable time of a sense amplifier SA.
The DRAM's column address decoder has a predecoder 116 and a Y-address decoder 118. In response to the FY pulse, predecoder 116 uses a column address signal BY.sub.j from the Y-address buffer 102 to form a predecoded column address signal AY.sub.j and applies it to Y-address decoder 118. Y-address decoder 118 decodes the column address signal BY.sub.j and activates the Y-address line YS.sub.j for the column indicated by signals BY.sub.j and AY.sub.j for an interval determined by the FY pulse.
Activating Y-address line YS.sub.j turns on an output transfer gate TR of the sense amplifier SA.sub.j connected to YS.sub.j, and the complementary readout data pair IO, IO.sub.-- that have been amplified by this sense amplifier SA.sub.j are respectively output to the data input/output lines IO and data input/output complementary line IO.sub.-- (FIG. 5(K)).
Also, an IO switch 120 of the memory array external unit that is connected to the sense amplifier SA.sub.j is also turned on, and the memory readout data IO, IO.sub.-- from sense amplifier SA.sub.j are sent to main amplifiers 122 via IO switch 120, memory array external data input/output line MIO and its complementary line MIO.sub.--, and a node EQ.
On the other hand, ATD circuit 104 responds to internal ATD pulse ATD by outputting an MA pulse shown in FIG. 5(J) to activate main amplifier 122 and an MAEQ pulse shown in FIG. 5(H) for blocking the amplification operation by equalizing (shorting) a prescribed node EQ within main amplifier 122.
When signal MAEQ falls, main amplifier 122 begins amplifying the data IO, IO.sub.-- read out by sense amp SA.sub.j and outputs corresponding readout data GIO, GIO.sub.-- at specified voltage levels as shown in FIG. 5(L). When the MA signal cuts off, main amplifier 122 is deactivated and the amplified memory readout data GIO, GIO.sub.-- is latched as the data signal DQ in an output buffer 124 as shown in FIG. 5(M).
In a write operation, the data to be written to the DRAM is sent to sense amplifiers SA from a prescribed data transmission circuit (not shown) via main amplifier 122, and from there is written to the desired memory cell MC through the bit line BL.
In FIG. 6, shows Y-address decoder 118 for the case in which memory array 100 has 512 Y-address lines. In this example, there are 64 column decoders DEC.sub.0 -DEC.sub.63 arranged in parallel and grouped into eight blocks BL.sub.0 -BL.sub.7. Each column decoder DEC.sub.n has its output terminals coupled to eight Y-address lines YS.
The column address signal AY from predecoder 116 comprises first, second, and third partial address signals AY0.sub.0-7, AY3.sub.0-7, and AY6.sub.0-7, each having 8 bits. In each of these partial address signals (AY0.sub.0-7, AY3.sub.0-7, AY6.sub.0-7), only one of the eight bits, for example, AY0.sub.3, AY3.sub.5, AY6.sub.1, is at a logic level of 1, and the remaining bits are 0. As a result, starting from the right, AY6.sub.1 indicates decoder block BL.sub.1, AY3.sub.5 the fifth column decoder DEC.sub.5 in block BL1, and AY0.sub.3 the third AY-address line YA3
The circuit construction of a conventional column decoder DEC is shown in FIG. 7. This column decoder is constructed of eight NMOS transistors K.sub.0 -K.sub.7, PMOS transistors U.sub.0 -U.sub.7, and inverter drivers D.sub.0 -D.sub.7, respectively, and the two NMOS transistors 130, 132.
The address bits AY0.sub.0 -AY0.sub.7 of the first partial address signals AY0.sub.0-7 are respectively applied to the gate terminals of NMOS transistors K.sub.0 -K.sub.7. The drain terminals of the NMOS transistors K.sub.0 -K.sub.7, along with being connected to the respective input terminals of the drivers D.sub.0 -D.sub.7, are connected to the power supply voltage V.sub.cc terminal of, for example, 3.3 V, through the respective PMOS transistors U.sub.0 -U.sub.7. The source terminals of NMOS transistors K.sub.0 -K.sub.7 are connected to the power supply voltage V.sub.ss terminal of, for example, 0 V, through the common NMOS transistors 130, 132.
The corresponding address bits AY3.sub.p (p=0-7) within the second partial address signal AY3.sub.0-7 are applied to the gate terminal of the NMOS transistor 130. The corresponding address bits AY6.sub.q (q=0-7) within the third partial address signal AY6.sub.0-7 are applied to the gate terminal of the NMOS transistor 132. These address bits AY3.sub.p, AY3.sub.q serve as enable signals for selecting this column decoder.
For the convenience of explanation, the eight Y-address lines that are respectively connected to the output terminals of the drivers D.sub.0 -D.sub.7 in this column decoder are called YS.sub.0 -YS.sub.7.
As for the PMOS transistors U.sub.0 -U.sub.7 in this column decoder, their respective gate terminals are connected to the power supply voltage V.sub.ss at the L level (0 V), and are always on.
In the interval in which the column address signal AY.sub.j is not applied, or even when a column address signal AY.sub.j is applied, to the extent that at least one of the enable signals (address bits) Ay3.sub.p, Ay6.sub.q is at a logic level of 0 (L level), in other words, to the extent that this column decoder is not selected, at least one of the common transistors 130, 132 is in off, and all of the nodes E.sub.0 -E.sub.7 between the drain terminals of NMOS transistors K.sub.0 -K.sub.7 and the drivers D.sub.0 -D.sub.7 are precharged to a logic level of 1 (H level). Therefore, the output voltage of all of the drivers D.sub.0 -D.sub.7 are at the L level, and all of the Y-address lines YS.sub.0 -YS.sub.7 are maintained in the disabled state.
In the event that the column address signal AY.sub.j is applied to the memory access, and both enable signals (address bits) AY3.sub.p, AY6.sub.q are at a logic level of 1 (H level), whichever one of the NMOS transistors K.sub.j that receives a bit AY.sub.j at a logic level of 1 (H level) within the address bits AY.sub.0 -AY.sub.7 of the first partial address signal AY0.sub.0-7 at its gate terminal turns on. All of the other NMOS transistors K.sub.0 -K.sub.j-1, K.sub.j+1 -K.sub.7 remain off.
When this is done, the node E.sub.j is discharged through the NMOS transistor K.sub.j that is on and the common transistors 130, 132; as a result, the potential of this node E.sub.j goes to the L level and the output voltage of the driver D.sub.j begins to rise to the H level, and in this way, the Y-address line YS.sub.j is enabled. Since the other nodes E.sub.0 -E.sub.j-1, E.sub.j +1 -E.sub.7 are maintained at the H level, the output voltages of the drivers D.sub.0 -D.sub.j-1, D.sub.j+1 -D.sub.7 that are connected to these nodes remain at the L level, and the Y-address lines other than the Y-address line YS.sub.j of YS.sub.0 -YS.sub.j-, YS.sub.j+1 -YS.sub.7 all remain disabled.
When this memory access is completed and the column address signal AY.sub.j is cut, the NMOS transistor K.sub.j and the common transistors 130, 132 that have thus for been on are turned back off, and node E.sub.j is precharged to the H level by means of the power supply voltage V.sub.cc through the PMOS transistor U.sub.j that is always on. When the node E.sub.j has been pulled up to the H level, the output voltage of the driver D.sub.j goes to the L level, and the Y-address line YS.sub.j is disabled.
In the conventional decoders, when the selected node E.sub.j is discharged, a discharge current flows so as to feed through the PMOS transistor U.sub.j, NMOS transistor K.sub.j, and the common transistors 130, 132 between the voltage power supply terminals V.sub.cc and V.sub.ss. Because this discharge feed through flows every time memory access is carried out, the power consumption of the entire DRAM markedly increases.
Also, because the voltage of the threshold components is lowered in the respective NMOS transistor K.sub.j and the common transistors 130, 132 as a result of this current feedthrough, there is also concern that the voltage of the selected node E.sub.j will not be pulled down completely below the threshold value of the L level, and as a result, there is also concern that the feedthrough current will flow within the driver D.sub.j.
A typical circuit construction of the driver D is shown in FIG. 8. In this CMOS inverter, the NMOS transistor NT constitutes a drive element, and the PMOS transistor PT constitutes a load element. When the input (node E) is at the H level, the NMOS transistor NT is on, the PMOS transistors PT is off, and the output (YS) goes to the L level. When the input (node E) is at the L level, the NMOS transistor NT is off, the PMOS transistors PT is on, and the output (YS) goes to the H level. In either case, since both transistors NT, PT are in a complementary (mutually opposite) state, it comes to be expected that current does not flow.
However, in the conventional column decoder, when the selected node E.sub.j is not sufficiently lowered to the L level, in addition to the PMOS transistor PT being almost on, the NMOS transistor NT is also almost on, and current flows through both the transistors NT, PT. When this type of feedthrough current flows within the driver D, there is concern that transistor elements NT, PT will deteriorate and break down.
In order to prevent this feedthrough current within the driver D, the method for sufficiently increasing the threshold voltage of the NMOS transistor NT has been considered. However, with this method when the node E.sub.j is restored from the L level to the H level after memory access is completed, the inversion of the output voltage at the driver D.sub.j is delayed, the returning of the Y-address line YS.sub.j to the disabled state is delayed, and there is concern that duplicate selection of another Y-address line YS immediately after being enabled may occur, it cannot be considered a suitable method.
For this reason, conventionally, there was no way to deal with this type of situation other than finely turning the width and length of the channel in the NMOS transistor NT, and the circuit design and semiconductor manufacturing processes had to be subjected to stringent conditions.
Our invention was developed taking the problems of the prior art into consideration, and its purpose is to offer an address decoder that solves the problems of feedsthrough current or leakage current at their root causes, and realizes a large reduction in the power consumption.